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1 mhz to 10 ghz, 50 db dual log detector/controller preliminary technical data adl5519 rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features wide bandwidth: 1 mhz to 10 ghz dual-channel and channel difference outputs ports integrated accurately scaled temperature sensor 50 db dynamic range up to 8 ghz stability over temperature 0.5 db low noise measurement/controller output vout pulse response time: 8/10 ns (fall/rise) small footprint 5 mm x 5 mm lfcsp package supply operation: 3.0 v to 5.5 v @ 65 ma fabricated using high speed sige process applications rf transmitter pa setpoint control and level monitoring power monitoring in radiolink transmitters rssi measurement in base stations, wlan, wimax, radar antenna vswr monitor dual-channel wireless infrastructure radios general description the adl5519 is a dual-demodulating logarithmic amplifier, using the ad8317 core. it has the capability of accurately converting an rf input signal to a corresponding decibel-scaled output. the adl5519 provides accurately scaled, independent, logarithmic outputs of both rf measurement channels. difference output ports, which measure the difference between the two channels, are also available. the on-chip channel matching makes the log-amp channel difference outputs extremely stable with temperature and process variations. the device also includes a useful temperature sensor with an accurately scaled voltage proportional to temperature, specified over the device operating temperature range. the adl5519 maintains accurate log conformance for signals of 1 mhz to 8 ghz and provides useful operation to 10 ghz. the input dynamic range is typically 50 db (re: 50 ) with error less than 1 db. the adl5519 has 8/10 ns response time (fall time/rise time) that enables rf burst detection to a pulse rate of beyond 50 mhz. the device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. a supply of 3.0 v to 5.5 v is required to power the device. current consumption is typically 65 ma, and it decreases to 1 ma when the device is disabled. the device is capable of supplying four log-amp measurements simultaneously. linear-in-db measurements are provided at outa and outb, with conveniently scaled slopes of -22 mv/db. the log-amp difference between outa and outb is available as differential or single-ended signals at outp and outn. an optional voltage applied to vlvl provides a common mode reference level to offset outp and outn above ground. on-chip wide bandwidth output op amps are connected to accommodate flexible configurations that support many system solutions. the adl5519 can be easily configured to provide a control voltage to a power amplifier at any output pin. since the output can be used for controller applications, special attention has been paid to minimize wideband noise the adl5519 is fabricated on a sige bipolar ic process and is available in a 5 mm 5 mm, 32-lead lfcsp package for an operating temperature range of ?40 o c to +125 o c.. channel a log detector channel b log detector clpb vlvl vref adjb vpsb clpa temp vpsr adja inhb inlb comr pwdn inla inha vsta vstb outb fbkb outn outp fbka outa bias temp vpsa outb outa 25 26 27 28 29 30 31 32 comr comr com r com r 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 comr comr 25 26 27 28 29 30 31 32 nc nc figure 1. functional block diagram
adl5519 preliminary technical data rev. prb | page 2 of 27 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 specifications..................................................................................... 3 absolute maximum ratings............................................................ 9 esd caution.................................................................................. 9 pin configuration and function descriptions........................... 10 typical performance characteristics ........................................... 12 theory of operation ...................................................................... 13 using the adl5519 ........................................................................ 14 basic connections ...................................................................... 14 input signal coupling................................................................ 14 temperature sensor interface................................................... 14 power-down interface............................................................... 15 setpoint interface, vst[a, b] ................................................... 15 output interface, out[a, b] ................................................... 15 difference output, out[p, n]................................................. 15 measurement mode ................................................................... 16 controller mode......................................................................... 17 temperature compensation adjustment................................ 20 device calibration and error calculation.............................. 20 altering the slope....................................................................... 21 output filtering.......................................................................... 21 basis for error calculations ...................................................... 21 evaluation board ............................................................................ 23 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27
preliminary technical data adl5519 rev. prb | page 3 of 27 specifications v pos = 5 v, c lpf = 1000 pf, t a = 25 c, 52.3 termination resistor at inhi, unless otherwise noted. table 1. parameter conditions min typ max unit signal input interface inh[a, b] (pins 19. 24) specified frequency range 0.001 10 ghz dc common-mode voltage v pos C 0.6 v measurement mode out[a, b] (pins 12, 7) shorted to vst[a,b] (pin 13, 6), out[p, n] (pins 10, 9) shorted to fbk[a, b] [pins 11, 8] respectively, sinusoidal input signal, error referred to best fit line using linear regression @ p inh[a, b] = ?40 dbm and ?20 dbm, t a = +25 c f = 100 mhz adja = adjb = tbd to gnd input impedance tbd ||pf out[a, b] 1 db dynamic range t a = +25 c 50 db ?40 c < t a < +85 c 46 db ?40 c < t a < +125 c tbd db out[a, b] maximum input level 1 db error ?3 dbm out[a, b] minimum input level 1 db error ?53 dbm out[a, b, p, n] slope tbd ?22 tbd mv/db out[a, b] intercept tbd 15 tbd dbm output voltage - high power in pins out[a, b] @ p inh[a, b] = ?10 dbm tbd 0.58 tbd v output voltage - low power in pins out[a, b] @ p inh[a, b] = ?40 dbm tbd 1.27 tbd v temperature sensitivity deviation from out[a, b] @ 25c ?40c < t a < 85c; p inh[a, b] = ?10 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?40 dbm tbd db outp-outn dynamic gain range 1 db error tbd db ?40c < t a < 85c tbd db temperature sensitivity outp-outn dynamic gain range tbd ?40c < t a < 85c; p inh[a, b] = ?10 dbm, ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?25 dbm, ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?40 dbm, ?25 dbm tbd db input a to input b isolation tbd db input a to outb isolation freq separation = 1 khz tbd input b to outa isolation p inhb = ?50 dbm, outb = outb pinhb 1 db tbd db p inha = ?50 dbm, outa = outa pinha 1 db tbd db f = 900 mhz adja = adjb = tbd to gnd input impedance tbd ||pf out[a, b] 1 db dynamic range t a = +25 c 50 db ?40 c < t a < +85 c 46 db ?40 c < t a < +125 c tbd out[a, b] maximum input level 1 db error ?3 dbm out[a, b] minimum input level 1 db error ?53 dbm out[a, b, p, n] slope tbd ?22 tbd mv/db out[a, b] intercept tbd 15 tbd dbm output voltage - high power in pins out[a, b] @ p inh[a, b] = ?10 dbm tbd 0.58 tbd v output voltage - low power in pins out[a, b] @ p inh[a, b] = ?40 dbm tbd 1.27 tbd v
adl5519 preliminary technical data rev. prb | page 4 of 27 parameter conditions min typ max unit temperature sensitivity deviation from out[a, b] @ 25c 25c < t a < 85c; p inh[a, b] = ?10 to -15 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -15 dbm .25 tbd db 25c < t a < 85c; p inh[a, b] = ?10 to -40 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -40 dbm .5 tbd db outp-outn dynamic gain range 1 db error tbd db ?40c < t a < 85c tbd db temperature sensitivity outp-outn dynamic gain range tbd 25c < t a < 85c; p inh[a, b] = ?10 to -15 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -15 dbm .25 tbd db 25c < t a < 85c; p inh[a, b] = ?10 to -40 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -40 dbm .5 tbd db input a to input b isolation tbd db input a to outb isolation freq separation = 1 khz tbd input b to outa isolation p inhb = ?50 dbm, outb = outb pinhb 1 db tbd db p inha = ?50 dbm, outa = outa pinha 1 db tbd db f = 1.9 ghz adja = adjb = tbd to gnd input impedance 950||0.38 ||pf out[a, b] 1 db dynamic range t a = +25 c 50 db ?40 c < t a < +85 c 48 db ?40 c < t a < +125 c tbd out[a, b] maximum input level 1 db error ?4 dbm out[a, b] minimum input level 1 db error ?54 dbm out[a, b, p, n] slope tbd ?22 tbd mv/db out[a, b] intercept tbd 14 tbd dbm output voltage - high power in pins out[a, b] @ p inh[a, b] = ?10 dbm tbd 0.54 tbd v output voltage - low power in pins out[a, b] @ p inh[a, b] = ?40 dbm tbd 1.21 tbd v temperature sensitivity deviation from out[a, b] @ 25c 25c < t a < 85c; p inh[a, b] = ?10 to -15 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -15 dbm .25 tbd db 25c < t a < 85c; p inh[a, b] = ?10 to -40 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -40 dbm .5 tbd db outp-outn dynamic gain range 1 db error tbd db ?40c < t a < 85c tbd db temperature sensitivity outp-outn dynamic gain range tbd 25c < t a < 85c; p inh[a, b] = ?10 to -15 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -15 dbm .25 tbd db 25c < t a < 85c; p inh[a, b] = ?10 to -40 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -40 dbm .5 tbd db input a to input b isolation tbd db input a to outb isolation freq separation = 1 khz tbd input b to outa isolation p inhb = ?50 dbm, outb = outb pinhb 1 db tbd db p inha = ?50 dbm, outa = outa pinha 1 db tbd db f = 2.2 ghz adja = adjb = tbd to gnd input impedance tbd ||pf out[a, b] 1 db dynamic range t a = +25 c 50 db ?40 c < t a < +85 c 47 db ?40 c < t a < +125 c tbd
preliminary technical data adl5519 rev. prb | page 5 of 27 parameter conditions min typ max unit out[a, b] maximum input level 1 db error ?5 dbm out[a, b] minimum input level 1 db error ?55 dbm out[a, b, p, n] slope ?22 mv/db out[a, b] intercept 14 dbm output voltage - high power in pins out[a, b] @ p inh[a, b] = ?10 dbm 0.53 v output voltage - low power in pins out[a, b] @ p inh[a, b] = ?40 dbm 1.20 v temperature sensitivity deviation from out[a, b] @ 25c 25c < t a < 85c; p inh[a, b] = ?10 to -15 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -15 dbm .25 tbd db 25c < t a < 85c; p inh[a, b] = ?10 to -40 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -40 dbm .5 tbd db outp-outn dynamic gain range 1 db error tbd db ?40c < t a < 85c tbd db temperature sensitivity outp-outn dynamic gain range tbd 25c < t a < 85c; p inh[a, b] = ?10 to -15 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -15 dbm .25 tbd db 25c < t a < 85c; p inh[a, b] = ?10 to -40 dbm .25 tbd db -20c < t a <25c; p inh[a, b] = ?10 to -40 dbm .5 tbd db input a to input b isolation tbd db input a to outb isolation freq separation = 1 khz tbd input b to outa isolation 1 p inhb = ?50 dbm, outb = outb pinhb 1 db tbd db p inha = ?50 dbm, outa = outa pinha 1 db tbd db f = 3.6 ghz adja = adjb = tbd to gnd input impedance tbd ||pf out[a, b] 1 db dynamic range t a = +25 c 42 db ?40 c < t a < +85 c 40 db ?40 c < t a < +125 c tbd out[a, b] maximum input level 1 db error ?6 dbm out[a, b] minimum input level 1 db error ?48 dbm out[a, b, p, n] slope ?22 mv/db out[a, b] intercept 11 dbm output voltage - high power in pins out[a, b] @ p inh[a, b] = ?10 dbm 0.47 v output voltage - low power in pins out[a, b] @ p inh[a, b] = ?40 dbm 1.16 v temperature sensitivity deviation from out[a, b] @ 25c ?40c < t a < 85c; p inh[a, b] = ?10 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?40 dbm tbd db outp-outn dynamic gain range 1 db error tbd db ?40c < t a < 85c tbd db temperature sensitivity outp-outn dynamic gain range tbd ?40c < t a < 85c; p inh[a, b] = ?10 dbm, ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?25 dbm, ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?40 dbm, ?25 dbm tbd db input a to input b isolation tbd db input a to outb isolation freq separation = 1 khz tbd input b to outa isolation 2 p inhb = ?50 dbm, outb = outb pinhb 1 db tbd db p inha = ?50 dbm, outa = outa pinha 1 db tbd db
adl5519 preliminary technical data rev. prb | page 6 of 27 parameter conditions min typ max unit f = 5.8 ghz adja = adjb = tbd to gnd input impedance tbd ||pf out[a, b] 1 db dynamic range t a = +25 c 50 db ?40 c < t a < +85 c 48 db ?40 c < t a < +125 c tbd out[a, b] maximum input level 1 db error ?4 dbm out[a, b] minimum input level 1 db error ?54 dbm out[a, b, p, n] slope ?22 mv/db out[a, b] intercept 16 dbm output voltage - high power in pins out[a, b] @ p inh[a, b] = ?10 dbm 0.59 v output voltage - low power in pins out[a, b] @ p inh[a, b] = ?40 dbm 1.27 v temperature sensitivity deviation from out[a, b] @ 25c ?40c < t a < 85c; p inh[a, b] = ?10 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?40 dbm tbd db outp-outn dynamic gain range 1 db error tbd db ?40c < t a < 85c tbd db temperature sensitivity outp-outn dynamic gain range tbd ?40c < t a < 85c; p inh[a, b] = ?10 dbm, ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?25 dbm, ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?40 dbm, ?25 dbm tbd db input a to input b isolation tbd db input a to outb isolation freq separation = 1 khz tbd input b to outa isolation 3 p inhb = ?50 dbm, outb = outb pinhb 1 db tbd db p inha = ?50 dbm, outa = outa pinha 1 db tbd db f = 8 ghz adja = adjb = tbd to gnd input impedance tbd ||pf out[a, b] 1 db dynamic range t a = +25 c 44 db ?40 c < t a < +85 c db ?40 c < t a < +125 c out[a, b] maximum input level 1 db error ?2 dbm out[a, b] minimum input level 1 db error ?46 dbm out[a, b, p, n] slope ?22 mv/db out[a, b] intercept 21 dbm output voltage - high power in pins out[a, b] @ p inh[a, b] = ?10 dbm 0.7 v output voltage - low power in pins out[a, b] @ p inh[a, b] = ?40 dbm 1.39 v temperature sensitivity deviation from out[a, b] @ 25c ?40c < t a < 85c; p inh[a, b] = ?10 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?40 dbm tbd db outp-outn dynamic gain range 1 db error tbd db ?40c < t a < 85c tbd db temperature sensitivity outp-outn dynamic gain range tbd ?40c < t a < 85c; p inh[a, b] = ?10 dbm, ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?25 dbm, ?25 dbm tbd db ?40c < t a < 85c; p inh[a, b] = ?40 dbm, ?25 dbm tbd db input a to input b isolation tbd db input a to outb isolation freq separation = 1 khz tbd
preliminary technical data adl5519 rev. prb | page 7 of 27 parameter conditions min typ max unit input b to outa isolation p inhb = ?50 dbm, outb = outb pinhb 1 db tbd db p inha = ?50 dbm, outa = outa pinha 1 db tbd db output interface out[a, b] (pins 12, 7), out[p, n] (pins 10, 9) out[a, b] voltage range min vst[a, b] = tbd rfin = open rl 240 : to ground tbd v vst[a, b] = 0v rfin = open rl 240 : to ground tbd v out[p, n] output out[a, b] = out[p, n] vlvl out[p, n] voltage range min fbk[a, b] = tbd rfin = open rl 240 : to ground tbd v fbk[a, b] = 0v rfin = open rl 240 : to ground tbd v source/sink current output held at 1v to 1% change 2.2 ma small signal bandwidth rfin = ?10 dbm, from clp[a,b] to out[a,b] tbd mhz output noise rf input = 2.2 ghz, C10 dbm, f noise = 100 khz, c lp[a,b] = open tbd nv/ hz fall time input level = no signal to C10 dbm, 90% to 10%, c lp[a,b] = 8 pf tbd ns fall time input level = no signal to C10 dbm, 90% to 10%, c lp[a,b] = open; tbd ns rise time input level = ?10 dbm to no signal, 10% to 90%, c lp[a, b] = 8 pf tbd ns rise time input level = ?10 dbm to no signal, 10% to 90%, c lp[a,b] = open, tbd ns video bandwidth (or envelope bandwidth) 50 mhz setpoint interface vst[a, b] (pins 13, 6) nominal input range input level = 0 dbm, measurement mode 0.5 v input level = C50 dbm, measurement mode 1.75 v logarithmic scale factor ?45 db/v logarithmic intercept tbd input resistance input level = ?20 dbm, controller mode, vst[a,b] = 1 v 40 k : difference level adjust vlvl (pin 4) voltage range out[p, n] = fbk[a, b] tbd v out[p, n] voltage range out[p, n] = fbk[a, b] tbd v input impedance tbd : ||pf temperature compensation adj[a, b] (pins 17, 2) input resistance adj[a, b] = 0.9 v, sourcing 50 a 13 k : disable threshold voltage adj[a, b] = open v pos C 0.4 v voltage reference vref (pin 3) output voltage 1.15 v temperature sensitivity ?40 q c < t a < +85 q c tbd mv/ o c current limit source/sink 3/3 ma temperature reference temp (pin 15) output voltage 1.3 v temperature sensitivity ?40 q c < t a < +125q c 4.5 mv/ o c current limit source/sink 5/40 ma/ua power-down interface pin pwdn logic level to enable logic lo enables tbd v logic level to disable logic hi disables tbd v input current logic hi pwdn = 5 v tbd a logic lo pwdn = 0 v tbd a enable time pwdn lo to outa/outb at 100% final value, c lpa/b = open, c hpa/b = 10 nf, rf in = 0 dbm tbd s
adl5519 preliminary technical data rev. prb | page 8 of 27 parameter conditions min typ max unit disable time pwdn hi to outa/outb at 10% final value, c lpa/b = open, c hpa/b = 10nf, rf in = 0 dbm tbd s power interface vps[a, b, r] (pins 18, 1, 16) supply voltage 3.0 5.5 v quiescent current 65 ma vs. temperature ?40 c t a +125 c tbd a/c disable current adj[a,b] = pwdn = vpos 1 ma
preliminary technical data adl5519 rev. prb | page 9 of 27 absolute maximum ratings table 2. parameter rating supply voltage: vpsa, vpsb, vpsr 5.7 v v set voltage: vsta, vstb 0 to v pos input power (single-ended, re: 50 ) inha, inla, inhb, inlb 12 dbm internal power dissipation ja 55c/w maximum junction temperature 165c operating temperature range ?40c to +125c storage temperature range ?65c to +150c lead temperature (soldering 60 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
adl5519 preliminary technical data rev. prb | page 10 of 27 pin configuration and fu nction descriptions vsta clpa temp vpsr adja vpsa outa fbka outp outn fbkb outb vstb clpb vlvl vref adjb vpsb adl5519 top view (not to scale) pin 1 indicator nc = no connect 1 comr 2 comr 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 com r com r nc nc inhb inlb comr pwdn inla inha comr comr figure 2. pin configuration table 3. pin function descriptions pin name description 1 comr common for differenc e output and temp sensor 2 comr common for differenc e output and temp sensor 3 vpsb positive supply for channel b. must be the same as vps[a/r]. apply 3.0v to 5.5v supply voltage. 4 adjb dual function pin. channel b temperature adjust. connect a resistor to ground to vary temperature compensation. connect to vps[a/ b/r] to power down channel b. 5 vref 1.15v voltage reference 6 vlvl dc common mode adjust for difference output 7 clpb loop filter pin for channel b 8 vstb setpoint control input for channel b 9 nc no connect 10 outb output voltage for channel b 11 fbkb difference op-amp feedback pin 12 outn difference output (outb - outa + vlvl) 13 outp difference output (outa - outb + vlvl) 14 fbka difference op-amp feedback pin 15 outa output voltage for channel a 16 nc no connect 17 vsta setpoint control input for channel a 18 clpa loop filter pin for channel a 19 temp temp sensor output (1.3v with 4.5mv/ o c slope) 20 vpsr positive supply for difference output and temperature sensor. must be the same as vps[a/b]. apply 3.0v to 5.5v supply voltage. 21 adja dual function pin. channel a temperature adjust. connect a resistor to ground to vary temperature compensation. connect to vps[a/ b/r] to power down channel a. 22 vpsa positive supply for channel a. must be the same as vps[b/r]. apply 3.0v to 5.5v supply voltage. 23 comr common for differenc e output and temp sensor 24 comr common for differenc e output and temp sensor 25 inha ac coupled rf input for channel a 26 inla ac coupled rf common for channel a 27 comr common for differenc e output and temp sensor 28 pwdn power down for differe nce output and temp sensor
preliminary technical data adl5519 rev. prb | page 11 of 27 29 comr common for differenc e output and temp sensor 30 comr common for differenc e output and temp sensor 31 inlb ac coupled rf common for channel b 32 inhb ac coupled rf input for channel b paddle internally connected to comr
adl5519 preliminary technical data rev. prb | page 12 of 27 typical performance characteristics v p = 5 v; t a = +25c, C40c, +85c; clpa/b = open. colors: +25c black, C40c blue, +85c red. figure 3: out[a, b] voltage and log conformance vs. input amplitude at 450 mhz, typical device, adj[a, b] = 0 v, sine wave, differential drive, figure 4: distribution of out[a, b] voltage and error over temperature after ambient normalization vs. input amplitude for at least 30 devices from multiple lots, frequency = 450 mhz, adj[a, b] = 0 v, sine wave, differential drive figure 5: distribution of [outa C outb] gain vs. inpu t amplitude over temperature for at least 30 devices from multiple lots, frequency = 450 mhz, adj[a, b] = 0 v, sine wave, differential drive figure 6: out[p, n]gain and log conformance vs. input amplitude at 450 mhz, typical device, adj[a, b] = 0 v, sine wave, differential drive (note that the outp and outn error curves overlap) figure 7: distribution of [outp ? outn] gain and error over temperature after ambient normaliz ation vs. input amplitude for at least 30 devices from multiple lots, frequency = 450 mhz, adj[a, b] = 0 v, sine wave, differential drive, p in ch. b = ?25 dbm, channel a swept figure 8: out[a, b] voltage and log conformance vs. input amplitude at 880 mhz, typical device, adj[a, b] = 0.5 v, sine wave, differential drive,
preliminary technical data adl5519 rev. prb | page 13 of 27 theory of operation the adl5519 is a dual-chann el 6-stage demodulating logarithmic amplifier, specifically designed for use in rf measurement and power control applications at frequencies up to 10 ghz. sharing much of its design with the ad8317 logarithmic detector/controller, the adl5519 maintains tight intercept variability vs. temperature over a 50 db range. each measurement channel offers equivalent performance to the ad8317. the complete circuit block diagram is shown in figure 9 . channel a log detector channel b log detector clpb vlvl vref adjb vpsb clpa temp vpsr adja inhb inlb comr pwdn inla inha vsta vstb outb fbkb outn outp fbka outa bias temp vpsa outb outa 25 26 27 28 29 30 31 32 com r comr com r com r 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 comr comr 25 26 27 28 29 30 31 32 nc nc figure 9. block diagram each measurement channel is a fully differential design and uses a proprietary, high speed sige process, extending high frequency performance. figure 10 shows the basic diagram of the adl5519s channel a signal path, the functionality is identical for channel b. det det det det inha inla iv out a vsta clpa iv figure 10. single channel block diagram the maximum input with 1 db log-conformance error is typically 0 dbm (re: 50 ). the noise spectral density referred to the input is 1.15 nv/ hz, which is equivalent to a voltage of 118 v rms in a 10.5 ghz bandwidth or a noise power of ?66 dbm (re: 50 ). this noise spectral density sets the lower limit of the dynamic range. however, the low end accuracy of the adl5519 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. the common pin, comr, provides a quality low impedance connection to the printed circuit board (pcb) ground. the package paddle, which is internally connected to the comr pin, should also be grounded to the pcb to reduce thermal impedance from the die to the pcb. the logarithmic function is approximated in a piecewise fashion by six cascaded gain stages. (for a more comprehensive explanation of the logarithm approximation, please refer to the ad8307 data sheet, available at www.analog.com.) the cells have a nominal voltage gain of 9 db each and a 3 db bandwidth of 10.5 ghz. using precision biasing, the gain is stabilized over temperature and supply variations. the overall dc gain is high, due to the cascaded nature of the gain stages. an offset compensation loop is included to correct for offsets within the cascaded cells. at the output of each of the gain stages, a square- law detector cell is used to rectify the signal. the rf signal voltages are converted to a fluctuating differential current having an average value that increases with signal level. along with the six gain stages and detector cells, an additional detector is included at the input of each measurement channel,, providing a 50 db dynamic range in total. after the detector currents are summed and filtered, the following function is formed at the summing node: i d log 10 ( v in / v intercept ) where: i d is the internally set detector current. v in is the input signal voltage. v intercept is the intercept voltage (that is, when v in = v intercept , the output voltage would be 0 v, if it were capable of going to 0 v).
adl5519 preliminary technical data rev. prb | page 14 of 27 using the adl5519 basic connections the adl5519 is specified for operation up to 10 ghz; as a result, low impedance supply pins with adequate isolation between functions are essential. a power supply voltage of between 3.0 v and 5.5 v should be applied to vpsa, vpsb, and vpsr. power supply decoupling capacitors of 100 pf and 0.1 f should be connected close to these power supply pins. adl5519acpz exposed paddle clpa temp vpsr adja clpb vlvl vref adjb vpsb vsta vstb outb fbkb outn outp fbka outa vpsa 27 28 29 30 31 32 inhb inlb comr pwdn inla inha 25 26 3 4 5 6 7 8 1 2 comr comr comr comr 14 13 12 11 10 9 16 15 nc nc 22 21 20 19 18 17 24 23 comr comr inha c4 47nf c3 47nf vpsb c11 100pf c16 0.1 f r11 0 r10 0 r9 diff out + diff out ? r4 0 c8 100pf c15 0.1 f vpsa c7 100pf c12 0.1 f r3 0 v ps r see text r5 52.3 inhb c2 c1 47nf r6 52.3 47nf r7 r12 0 setpoint voltage b output voltage b r20 0 r2 1k r1 1k r8 0 setpoint voltage b output voltage b r21 0 0 see text see text see text 0 see text figure 11. basic connections the paddle of the lfcsp_vd package is internally connected to comr. for optimum thermal and electrical performance, the paddle should be soldered to a low impedance ground plane. input signal coupling the rf inputs (inha and inhb) are single-ended and must be ac-coupled. inla and inlb (input common) should be ac-coupled to ground. suggested coupling capacitors are 47 nf ceramic 0402-style capacitors for input frequencies of 1 mhz to 10 ghz. the coupling capacitors should be mounted close to the inha[inhb] and inla[inlb} pins. the coupling capacitor values can be increased to lower the input stages high-pass cutoff frequency. the high-pass corner is set by the input coupling capacitors and the internal 10 pf high-pass capacitor. the dc voltage on inha[inhb] and inla[inlb] is about one diode voltage drop below the supply voltage. vpsa 2k a = 9db 18.7k 18.7k current gm stage inla inha offset comp 5pf 5pf first gain stage figure 12. single channel input interface while the input can be reactively matched, in general this is not necessary. an external 52.3 shunt resistor (connected on the signal side of the input coupling capacitors, as shown in figure 11 ) combines with the relatively high input impedance to give an adequate broadband 50 match. the coupling time constant, 50 c c /2, forms a high-pass corner with a 3 db attenuation at f hp = 1/(2 50 c c ), where c1 = c2 = c c . using the typical value of 47 nf, this high pass corner will be ~68 khz. in high frequency applications, f hp should be as large as possible to minimize the coupling of unwanted low frequency signals. in low frequency applications, a simple rc network forming a low-pass filter should be added at the input for similar reasons. this should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency. temperature sensor interface the adl5519 provides a temperature sensor output capable of driving about 1.6 ma. the temperature scaling factor of the output voltage is approximately 2 mv/c. the typical absolute voltage at 25c is ~620 mv. tem p v psr internal v ptat 12k 4k comr figure 13. temp interface simplified schematic
preliminary technical data adl5519 rev. prb | page 15 of 27 power-down interface the operating and stand-by currents for the adl5519 at 25c are approximately 65 ma and 1 ma, respectively. the pwdn and adj[a,b] pins are connected to the base of and npn transistor to force a power down condition. typically, when pwdn is pulled >2.5 v, the adl5519 is powered down from 65ma to <1ma. the output reaches to within 0.1 db of its steady-state value in about 1.6 s; the reference voltage is available to full accuracy in a much shorter time. this wake-up response time varies depending on the input coupling network and the capacitance at pins clp[a, b]. the individual log channels can be disabled by installing a 0 pull up resistor from adj[a,b] to vps[a,b]. setpoint interface, vst[a, b] the v set input drives the high impedance (20 k) input of an internal op amp. the v set voltage appears across the internal 1.5 k resistor to generate i set . when a portion of v out is applied to vset, the feedback loop forces ? i d log 10 ( v in / v intercept ) = i set . if v set = v out /2x, then i set = v out /(2x 1.5 k ). the result is v out = (? i d 1.5 k 2x) log 10 ( v in / v intercept ) 05541-025 1.5k the slope is given by C i d 2x 1.5 k = ?22 mv/db x. for example, if a resistor divider to ground is used to generate a v set voltage of v out /2, then x = 2. the slope is set to ?880 v/decade or ?44 mv/db. output interface, out[a, b] the out[a,b] pin is driven by a pnp output stage. an internal 10 resistor is placed in series with the output and the out[a,b] pin. the rise time of the output is limited mainly by the slew on clp[a,b]. the fall time is an rc- limited slew given by the load capacitance and the pull- down resistance at out[a,b]. there is an internal pull- down resistor of 1.6 k. a resistive load at out[a,b] is placed in parallel with the internal pull-down resistor to provide additional discharge current. out[a, b] v ps[a, b] clp[a,b] 1.2k out[a, b] can source and sink up to 2.2 ma. difference output, out[p, n] the adl5519 incorporates two operational amplifiers with rail-to-rail output capability to provide a channel difference output. outp vpsr vlvl fbka comr outa outb 05334-030 outn vpsr vlvl fbkb comr outb outa 1k as in the case of the output drivers for out[a, b], the output stages have the capability of driving 2.2 ma. outa and outb are internally connected through 1 k resistors to the inputs of each op amp. the pin vlvl is connected to the positive terminal of both op amps through 1 k resistors to provide level shifting. the negative feedback terminal is also made available through a 1 k resistor. the input impedance of vlvl is 1 k and fbk[a, b] is 2 k. see figure 17 for the connections of these pins. fbk out out fbk b n p a outb outa 27 28 29 30 figure 17. op amp connections (all resistors are 1 k 20%) if outp is connected to fbka, then outp is given as outp = outa C outb + vlvl (9) if outn is connected to fbkb, then outn is given as outn = outb C outa + vlvl (10)
adl5519 preliminary technical data rev. prb | page 16 of 27 in this configuration, all four measurements, out[a, b, p, n], are made available simultaneously. a differential output can be taken from outp ? outn, and vlvl can be used to adjust the common-mode level for an adc connection. measurement mode the adl5519 requires a single supply of 3.0 v to 5 v. the supply is connected to the three supply pins, vpsa, vpsb, and vpsr. each pin should be decoupled using the two capacitors with values equal or similar to those shown in figure 19 . these capacitors must provide a low impedance over the full frequency range of the input, and they should be placed as close as possible to the positive supply pins. two different capacitors are used in parallel to provide a broadband ac short to ground. the device is placed in measurement mode by connecting outa and/or outb to vsta and/or vstb, respectively. as seen in figure 18 , the adl5519 has an offset voltage, a negative slope, and a v out[a,b] measurement intercept at the high end of its input signal range. figure 18. typical output voltage vs. input signal, single channel the output voltage vs. input signal voltage of the adl5519 is linear-in-db over a multidecade range. the equation for this function is of the form v out = x v slop e/ dec log 10 ( v in / v intercept ) = (1) x v slope/db 20 log 10 ( v in / v intercept ) (2) where: x is the feedback factor in v set = v out /x. v slope/dec is nominally C440 mv/decade or ?22 mv/db. v intercept is the x-axis intercept of the linear-in-db portion of the v out vs. v in curve ( figure 18 ). v intercept is +2 dbv for a sinusoidal input signal. an offset voltage, v offset , of 0.35 v is internally added to the detector signal, so that the minimum value for v out is x v offset . so for x = 1, minimum v out is 0.35 v. the slope is very stable vs. process and temperature variation. when base-10 logarithms are used, v slope/decade represents the volts/decade. a decade corresponds to 20 db; v slope/decade /20 = v slope/db represents the slope in volts/db. as noted in equation 1 and equation 2, the v out voltage has a negative slope. this is also the correct slope polarity to control the gain of many power amplifiers in a negative feedback configuration. because both the slope and intercept vary slightly with frequency, it is recommended to refer to the specifications section for application-specific values for slope and intercept. although demodulating log amps respond to input signal voltage, not input signal power, it is customary to discuss the amplitude of high frequency signals in terms of power. in this case, the charac- teristic impedance of the system, z 0 , must be known to convert voltages to their corresponding power levels. the following equations are used to perform this conversion: p (dbm) = 10 log 10 ( v rms 2 /( z 0 1 mw)) (3) p (dbv) = 20 log 10 ( v rms /1 v rms ) (4) p (dbm) = p (dbv) ? 10 log 10 ( z 0 1 mw/1 v rms 2 ) (5) for example, p intercept for a sinusoidal input signal expressed in terms of dbm (decibels referred to 1 mw), in a 50 system is p intercept (dbm) = p intercept (dbv) C 10 log 10 ( z 0 1 mw/1 v rms 2 ) = (6) +2 dbv ? 10 log 10 (5010 -3 ) = +15 dbm for a square wave input signal in a 200 system, p intercept = ?1 dbv ? 10 log 10 [(200 1 mw/1 v rms 2 )] = +6 dbm further information on the intercept variation dependence upon waveform can be found in the ad8313 and ad8307 data sheets. as the input signal to channel a and channel b are swept over their nominal input dynamic range of +10 dbm to ?50 dbm, the output swings from 0.5 v to 1.75 v. the voltages outa and outb are also internally applied to a difference amplifier with a gain of two. so as the db difference between ina and inb ranges from approximately ?30 db to +30 db, the difference voltage on outp and outn swings from 0.5 v to 1.75 v. input differences larger than 30 db can be measured as long as the absolute input level at ina and inb are within their nominal ranges of +10 dbm to ?50 dbm. however, measurement of large differences between ina and inb are affected by on-chip signal leakage. the common-mode level of outp and outn is set by the voltage applied to vlvl. these output can be easily biased up to a common-mode voltage of 2.5 v by connecting vref to vlvl. as the gain range is swept, outp swings from approximately 0.5 v to 1.75 v and outn swings from 1.75 v to 0.5 v.
preliminary technical data adl5519 rev. prb | page 17 of 27 adl5519acpz exposed paddle clpa temp vpsr adja clpb vlvl vref adjb vpsb vsta vstb outb fbkb outn outp fbka outa vpsa 27 28 29 30 31 32 inhb inlb comr pwdn inla inha 25 26 3 4 5 6 7 8 1 2 comr comr comr comr 14 13 12 11 10 9 16 15 nc nc 22 21 20 19 18 17 24 23 comr comr inha c4 47nf c3 47nf vpsb c11 100pf c16 0.1 f r11 0 r10 0 r9 diff out + diff out ? r4 0 c8 100pf c15 0.1 f vpsa c7 100pf c12 0.1 f r3 0 v psr see text r5 52.3 inhb c2 c1 47nf r6 52.3 47nf r7 r12 0 setpoint voltage b output voltage b r20 0 r2 1k r1 1k r8 0 setpoint voltage b output voltage b r21 0 0 see text see text see text 0 see text figure 19. basic connections for operation in measurement mode controller mode in addition to being a measurement device, the adl5519 can also be configured to measure and control signal levels. the adl5519 has two controller modes. each of the two log detectors can be separately configured to set and control the output power level of a variable gain amplifier (vga) or variable voltage attenuator (vva). alternatively, the two log detectors can be configured to measure and control the gain of an amplifier or signal chain. the channel difference outputs can be used for controlling a feedback loop to the adl5519s rf inputs. a capacitor connected between fbka and outp forms an integrator, keeping in mind that the on-chip 1 k feedback resistor forms a zero. (the value of the on-chip resistors can vary as much as 20% with manufac- turing process variation.) if channel a is driven and channel b has a feedback loop from outp through a pa, then outp integrates to a voltage value such that outb = ( outa + vlvl )/2 (11) the output value from outn may or may not be useful. it is given by outn = 0 v (12) for vlvl < outa/3, otherwise, outn = (3 vlvl C outa )/2 (13) if vlvl is connected to outa, then outb is forced to equal outa through the feedback loop. this flexibility provides the user with the capability to measure one channel operating at a given power level and frequency while forcing the other channel to a desired power level at another frequency. adja and adjb should be set to different voltage levels to reduce the temperature drift of the output measurement. the temperature drift will be statistical sum of the drift from channel a and channel b. as stated before, vlvl can be used to force the slaved channel to operate at a different power than the other channel. if the two channels are forced to operate at different power levels, then some static offset occurs due to voltage drops across metal wiring in the ic. if an inversion is necessary in the feedback loop, outn can be used as the integrator by placing a capacitor between outn
adl5519 preliminary technical data rev. prb | page 18 of 27 and outp. this changes the output equation for outb and outp to outb = 2 outa ? vlvl (14) for vlvl < outa/2, outn = 0 v (15) otherwise, outn = 2 vlvl C outa (16) the previous equations are valid when channel a is driven and channel b is slaved through a feedback loop. when channel b is driven and channel a is slaved, the above equations can be altered by changing outb to outa and outn to outp. automatic power control figure 20 shows how the device should be reconfigured to control output power . the rf input to the device is configured as before. a directional coupler taps off some of the power being generated by the vga (typically a 10 db to 20 db coupler is used). a power splitter can be used instead of a directional coupler if there are no concerns about reflected energy from the next stage in the signal chain. some additional attenuation may be required to set the maximum input signal at the adl5519 to be equal to the recommended maximum input level for optimum linearity and temperature stability at the frequency of operation. vsta and outa are no longer shorted together. outa now provides a bias or gain control voltage to the vga. the gain control sense of the vga must be positive and monotonic, that is, increasing voltage tends to increase gain. however, the gain control transfer function of the device does not need to be well controlled or particularly linear. if the gain control sense of the vga is negative, an inverting op amp circuit with a dc offset shift can be used between the adl5519 and the vga to keep the gain control voltage in the 0 v to 5 v range. vsta becomes the setpoint input to the system. this can be driven by a dac, as shown in figure 20 , if the output power is expected to vary, or it can simply be driven by a stable reference voltage if constant output power is required. this dac should have an output swing that covers the 0 v to 3.5 v range. the ad7391 and ad7393 serial-input and parallel-input 10-bit dacs provide adequate resolution (4 mv/bit) and an output swing up to 4.5 v. when vsta is set to a particular value, the adl5519 compares this value to the equivalent input power present at the rf input. if these two values do not match, outa increases or decreases in an effort to balance the system. the dominant pole of the error amplifier/integrator circuit that drives outa is set by the capacitance on pin clpa; some experimentation may be necessary to choose the right value for this capacitor. in general, clpa should be chosen to provide stable loop operation for the complete output power control range. if the slope (in db/v) of the gain control transfer function of the vga is not constant, clpa must be chosen to guarantee a stable loop when the gain control slope is at its maximum. on the other hand, clpa must provide adequate averaging to the internal low range squaring detector so that the rms computation is valid. larger values of clpa tend to make the loop less responsive. the relationship between vsta and the rf input follows from the measurement mode behavior of the device. for example, from figure 8 , which shows the measurement mode transfer function at 880 mhz, it can be seen that an input power of ?10 dbm yields an output voltage of 2.5 v. therefore, in controller mode, vsta should be set to 2.5 v, which results in an input power of ?10 dbm to the adl5519. adl5519 vga or vva (output power increases as v apc decreases) inha clpa inla 0.1 f 0.1 f see text vsta outa v apc dac 0v to 3.5v (0v to 4.9v available swing) p in p out attenuator 50 automatic gain control figure 21 shows how the adl5519 can be connected to provide automatic gain control to an amplifier or signal chain. additional pins are omitted for clarity. in this configuration, both log detectors are connected in measurement mode with appropriate filtering being used on clp[a, b]. outa, however, is also connected to the vlvl pin of the on-board difference amplifier. also, the outp output of the difference amplifier drives a variable gain element (either vva or vga) and is connected back to the fbka input via a capacitor so that it is operating as an integrator. assume that outa is much bigger than outb. because outa also drives vlvl, this voltage is also present on the noninverting input of the op amp driving outp. this results in a net current flow from outp through the integrating capacitor into the fbka input. this results in the voltage on outp decreasing. if the gain control transfer function of the vva/vga is negative, this increases the gain, which in turn increases the input signal to inhb. the output voltage on the integrator continues to
preliminary technical data adl5519 rev. prb | page 19 of 27 increase until the power on the two input channels is equal, resulting in a signal chain gain of unity. if a gain other than 0 db is required, an attenuator can be used in one of the rf paths, as shown in figure 21 . alternatively, power splitters or directional couplers of different coupling factors can be used. another convenient option is to apply a voltage on vlvl other than outa. refer to equation 11 and the controller mode section for more detail. if the vga/vva has a positive gain control sense, the outn output of the difference amplifier can be used with the integrating capacitor tied back to fbkb. the choice of the integrating capacitor affects the response time of the agc loop. small values give a faster response time but can result in instability, whereas larger values reduce the response time. note that in this mode, the capacitors on clpa and clpb, which perform the rms averaging function, must still be used and also affect the loop response time. channel a log detector channel b log detector clpb clpa vlvl inhb inlb inla inha vsta vstb outb fbkb outn outp fbka outa adl5519 c int diff out + 0.1 f 0.1 f attenuator vga/vva directional or power splitter directional or power splitter 50 0.1 f 0.1 f 50 figure 21. operation in controller mode for automatic gain control
preliminary technical data adl5519 rev. prb | page 20 of 27 temperature compensation adjustment the adl5519 has a highly stable measurement output with respect to temperature. however, when the rf inputs exceed a frequency of 600 mhz, the output temperature drift must be compensated for using adj[a, b] for optimal performance. proprietary techniques are used to compensate for the temper- ature drift. the absolute value of compensation varies with frequency and circuit board material. table 4 shows recommended voltages for adj[a, b] to maintain a temperature drift error of typically 0.5 db or better over the entire rated temperature range with the recommended baluns. table 4: recommended adj[a,b] voltage levels frequency recommended adj[a,b] voltage 50 mhz tbd 100 mhz tbd 900 mhz tbd 1.8 ghz tbd 1.9 ghz tbd 2.2 ghz tbd 3.6 ghz tbd 5.3 ghz tbd 5.8 ghz tbd 8 ghz tbd compensating the device for temperature drift using adj[a, b] allows for great flexibility. if the user requires minimum temper- ature drift at a given input power or subset of the dynamic range, the adj[a, b] voltage can be swept while monitoring out[a, b] over temperature. figure 22 shows the result of such an exercise. the value of adj[a, b] where the output has minimum movement (approximately 0.77 v for the example in figure 22 ) is the recommended voltage for adj[a, b] to achieve minimum temperature drift at a given power and frequency. figure 22. outa vs. adja over temp. pin = ?30 dbm, 1.9 ghz the adj[a, b] input has high input impedance. the input can be conveniently driven from an attenuated value of vref using a resistor divider, if desired. figure 23 shows a simplified schematic representation of the adj[a, b] interface. comr comr i comp adj[a,b] v tadj v ref adl5519 figure 23. adj[a, b] interface simplified schematic device calibration and error calculation the measured transfer function of the adl5519 at 2.14 ghz is shown in figure 24 . the figure shows plots of both output voltage vs. input power and calculated error vs. input power. as the input power varies from ?50 dbm to 0 dbm, the output voltage varies from 0.4 v to about 2.8 v. figure 24. transfer function at 2.14 ghz. because slope and intercept vary from device to device, board- level calibration must be performed to achieve high accuracy. the equation for output voltage can be written as v out = slope ( p in ? intercept ) where slope is the change in output voltage divided by the change in power (db), and intercept is the calculated power at which the output voltage would be 0 v. (note that intercept is a theoretical value; the output voltage can never achieve 0 v). in general, the calibration is performed by applying two known signal levels to the adl5519s input and measuring the corresponding output voltages. the calibration points are generally chosen to be within the linear-in-db operating range of the device (see the specifications section for more details). calculation of the slope and intercept is done using the equations: slope = ( v out1 ? v out2 )/( p in1 ? p in2 ) intercept = p in1 ? ( v out1 / slope )
preliminary technical data adl5519 rev. prb | page 21 of 27 once slope and intercept have been calculated, an equation can be written that will allow calculation of the input power based on the output voltage of the detector. p in ( unknown ) = (v out1 ( measured) / slope ) + intercept the log conformance error of the calculated power is given by error (db) = ( v out (measured) ? v out(ideal) )/ slope figure 24 includes a plot of the error at 25c, the temperature at which the log amp is calibrated. note that the error is not zero. this is because the log amp does not perfectly follow the ideal v out vs. p in equation, even within its operating region. the error at the calibration points (?43 dbm and ?23 dbm in this case) will, however, be equal to zero by definition. figure 24 also includes error plots for the output voltage at ?40c and +85 c. these error plots are calculated using the slope and intercept at 25c. this is consistent with calibration in a mass-production environment, where calibration at temperature is not practical. altering the slope none of the changes to operating conditions discussed so far affect the logarithmic slope, v slope , in equation 7. the slope can readily be altered by controlling the fraction of out[a, b] that is fed back to the setpoint interface at the vst[a, b] pin. when the full signal from out[a, b] is applied to vst[a, b], the slope assumes its nominal value of -22 mv/db. it can be increased by including a voltage divider between these pins, as shown in figure 25 . moderately low resistance values should be used to minimize scaling errors due to the approximately 40 k input resistance at the vst[a, b] pin. keep in mind that this resistor string also loads the output, and it eventually reduces the load-driving capabilities if very low values are used. equation 17 can be used to calculate the resistor values. r1 = r2' ( s d /-22 ? 1) (17) where: s d is the desired slope, expressed in mv/db. r2' is the value of r2 in parallel with 40 k. for example, using r1 = 1.65 k and r2 = 1.69 k ( r2' = 1.62 k), the nominal slope is increased to -44 mv/db. operating at a high slope is useful when it is desired to measure a particular section of the input range in greater detail. when the slope is raised by some factor, the loop capacitor, clp[a, b], should be raised by the same factor to ensure stability and to preserve a chosen averaging time. the slope can be lowered by placing a voltage divider after the output pin, following standard practice. out[a,b] adl5519 vst[a,b] r2 r1 v ou t figure 25. external network to raise slope output filtering accurate power detection for signals with rf bursts is achieved when the adl5519 is able to respond quickly to the change in rf power. for applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the clp[a,b] pin be left unconnected and free of any stray capacitance. the nominal output video bandwidth of 50 mhz can be reduced by connecting a ground-referenced capacitor (c flt ) to the clpf pin, as shown in figure 26 . this is generally done to reduce output ripple (at twice the input frequency for a symmetric input waveform such as sinusoidal signals). +4 out[a,b] clp[a,b] adl5519 3.5pf i log[a,b] c flt 1.5k c flt is selected using the following equation: () ? ? = bandwidth video c flt (10) the video bandwidth should typically be set to a frequency equal to about one-tenth the minimum input frequency. this ensures that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered. basis for error calculations the slope and intercept are derived using the coefficients of a linear regression performed on data collected in its central operating range. error is stated in two forms: (1) error from linear response to cw waveform and (2) output delta from 25c performance. the error from linear response to cw waveform is the decibel difference in output from the ideal output defined by the conversions gain and output reference. this is a measure of the linearity of the device response to both cw and modulated waveforms. the error in db is calculated by
adl5519 preliminary technical data rev. prb | page 22 of 27 error (db) = ( ) slope ppslope v z in out ?? where p z is the x-axis intercept expressed in dbm. this is analogous to the input amplitude that would produce an output of 0 v, if such an output was possible. error from the linear response to the cw waveform is not a measure of absolute accuracy, since it is calculated using the slope and intercept of each device. however, it verifies the linearity and the effect of modulation on the devices response. similarly, error from 25c performance uses the 25c performance of a given device and waveform type as the reference from which all other performance parameters shown alongside it are compared. it is predominantly (and most often) used as a measurement of output variation with temperature.
preliminary technical data adl5519 rev. prb | page 23 of 27 evaluation board table 5. evaluation board (rev. a) configuration options component function default conditions vpos, gnd1, gnd2, gnd3 supply and ground connections. gnd1, gnd2, gnd3 are internally connected together. not applicable r5, r6, c1, c2, c3, c4 input interface. the 52.3 resistor in positions r5 and r6 combine with the adl5519's internal input impedance to give a broadband input impedance of about 50 . capacitors c1, c2, c3, and c4 are dc-blocking capacitors. a reactive impedance match can be implemented by replacing r5[r6] with an inductor and c1[c3] and c2[c4] with appropriately valued capacitors. r5 = 52.3 (size 0402) c1 = 47 nf (size 0402) c2 = 47 nf (size 0402) r6 = 52.3 (size 0402) c3 = 47 nf (size 0402) c4 = 47 nf (size 0402) r14 temperature sensor interface: the temperature sensor output voltage is available at the test point labeled temp. r14 = 0 (size 0603) r13, r17, r18, r19, r27, r28, r29 temperature compensation interface. the internal temperature compensation network is optimized for input signals up to tbd ghz when the voltage applied to the adj[a,b] pin is tbd v. this circuit can be adjusted to optimize performance for other input frequencies by changing the value of this voltage. see table 4 for specific voltage levels. the pads for r27/r28 or r27/r29 can be used for voltage dividers to set the adj[a,b] voltages for temperature compensation at different frequencies. the individual log channels can be disabled by installing 0 resistors in positions r18 and r19 r13 = open (size 0603) r17 = open (size 0603) r18 = 0 (size 0603) r19 = 0 (size 0603) r27 = 0 (size 0603) r28 = open (size 0603) r29 = open (size 0603) r8, r12, r15, r16, r20, r21, r22, r23, c13, c14 output interfacemeasurement mode. in measurement mode, a portion of the output voltage is fed back to pin vsta[vstb] via r8[r12]. the magnitude of the slope of the outa[outb] output voltage response can be increased by reducing the portion of v outa [v outb ]that is fed back to vsta[vstb]. r20[r21} can be used as a back- terminating resistor or as part of a single-pole, low-pass filter. r8 = 0 (size 0603) r12 = 0 (size 0603) r15 = open (size 0603) r16 = open (size 0603) r20 = 0 (size 0603) r21 = 0 (size 0603) r22 = open (size 0603) r23 = open (size 0603) c13 = open (size 0603) c14 = open (size 0603) r8, r12, r22, r23 output interfacecontroller mode. in this mode, r8[r12] must be open. in controller mode, the adl5519 can control the gain of an external component. a setpoint voltage is applied to pin vsta[vstb], the value of which corresponds to the desired rf input signal level applied to the corresponding adl5519 rf input. a sample of the rf output signal from this variable-gain component is selected, typically via a directional coupler, and applied to adl5519 rf input. the voltage at pin outa[outb] is applied to the gain cont rol of the variable gain element. a control voltage is applied to pin vsta[vstb]. the magnitude of the control voltage can optionally be attenuated via the voltage divider comprising r8[r12] and r22[r23], or a capacitor can be installed in position r22[r23] to form a low-pass filter along with r8[r12]. r8 = 0 (size 0603) r12 = 0 (size 0603) r22 = open (size 0603) r23 = open (size 0603) r3, r4, r11, c7, c8 c11, c12, c15, c16 power supply decoupling. the nominal supply decoupling consists of a 100 pf filter capacitor placed physically close to the adl5519 and a 0.1 f capacitor placed nearer to each power supply input pin. r3 = 0 (size 0603) r4 = 0 (size 0603) r11 = 0 (size 0603) c7 = 100 pf (size 0603) c8 = 100 pf (size 0603) c11 = 100 pf (size 0603) c12 = 0.1 f (size 0603) c15 = 0.1 f (size 0603) c16 = 0.1 f (size 0603)
adl5519 preliminary technical data rev. prb | page 24 of 27 r1, r2, r9, r10 output interface C difference r1 = 1k (size 0603) r2 = 1k (size 0603) r9 = open (size 0603) r10 = open (size 0603) c9, c10 filter capacitor. the low-pass corner frequency of the circuit that drives pin outa[outb] can be lowered by placing a capacitor between clpa[clpb] and ground. increasing this capacitor increases th e overall rise/fall time of the adl5519 for pulsed input signals. see the output filtering section for more details. c9 = 100 pf (size 0603) c10 = 100 pf (size 0603)
preliminary technical data adl5519 rev. prb | page 25 of 27 vpsb c16 100pf c11 0.1 f r11 0 r17 open c5 0.1 f c6 open c10 100pf vref adjb r10 0 r9 diff out + diff out ? adl5519acpz exposed paddle r4 0 r14 open temp sensor c8 100pf c15 0.1 f clpa temp vpsr adja clpb vlvl vref adjb vpsb vsta vstb outb fbkb outn outp fbka outa vpsa vpsa c7 100pf c12 0.1 f r3 0 v psr r13 open adja c9 100pf 27 28 29 30 31 32 inha pwdn c4 47nf c3 47nf inhb inlb comr pwdn inla inha r5 52.3 inhb c2 c1 47nf r6 52.3 47nf r19 open r7 0 vlvl r12 0 setpoint voltage b output voltage b r22 open r20 r16 open c14 open 0 r2 1k r1 1k r8 0 setpoint voltage b output voltage b r23 open r21 r15 open c13 open 0 0 r18 open vpos r24 0 r25 0 r26 0 vpsa vpsb vpsr gnd1 gnd2 gnd3 25 26 3 4 5 6 7 8 1 2 comr comr comr comr 14 13 12 11 10 9 16 15 nc nc 22 21 20 19 18 17 24 23 comr comr adja adjb vref r28 open r29 open r27 0 figure 27. evaluation board schematic
preliminary technical data adl5519 rev. prb | page 26 of 27 figure 28. top side layout figure 29. top side silkscreen figure 30: bottom side layout figure 31: bottom side silkscreen
preliminary technical data adl5519 rev. prb | page 27 of 27 outline dimensions compliant to jedec standards mo-220-vhhd-2 1 32 8 9 25 24 17 16 2.85 2.70 sq 2.55 top view coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.20 min exposed pad (bot tom view) pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq figure 32. 32-lead lead frame chip scale package [lfcsp_vd] 5 mm x 5 mm body, very thin, dual lead (cp-32-8) dimensions shown in millimeters ordering guide model temperature package package description package option branding adl5519acpz-r7 1 ?40c to +85c 32-lead lfcsp_vd cp-32-8 tbd adl5519acpz-r2 1 ?40c to +85c 32-lead lfcsp_vd cp-32-8 tbd adl5519acpz-wp 1 , 2 ?40c to +85c 32-lead lfcsp_vd cp-32-8 tbd ADL5519-EVALZ 1 evaluation board 1 z = pb-free part. 2 wp = waffle pack.

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